Abstract
Orthogonal Frequency Division Multiplexing (OFDM) is a popular advanced communication technology for wireless local area network (WLAN) because it can effectively improve channel utilization and reduce inter-symbol interference (ISI) and inter-carrier interference (ICI) caused by multipath effect. Since FFT and IFFT is a core of OFDM technique, we design a low hardware complexity and high performance FFT/IFFT processor for multi-standard OFDM communications in this thesis. Because hardware requirement of various communication systems based on OFDM have similar architectures, we can add little extra hardware to improve the flexibility of hardware usage. In algorithms, we adopted radix-2/4/8 algorithm to reduce computational complexity and minimize required complex multipliers. In hardware implementation, we used three real multipliers to implement a complex multiplier and storage technique of eighth sine/cosine values in order to simplify required hardware. We also proposed a modified signal flow graph to be suitable for parallel processing, and then it can improve the performance of FFT/IFFT processor. Because of using parallel processing architecture, it required a lot of memory banks to cause large area and power consumption. Therefore, we utilized the multi-word length storage technique to minimize required memory banks. At finally, we used a Xilinx Spartan3 board to implement an 8k/4k/2k/1k/256/64-point FFT/IFFT processor. This processor consisted of 4-level parallel architecture、24 complex multipliers and 7 dual-port SRAM. The proposed structure can operate at 200MHz, and will be applied widely in high-speed signal processing.