Abstract
Wireless communication plays a significant role in people’s life nowadays, and the response to an ever-growing demand for multimedia data transmission, have spawned a variety of communications technologies, including multiple-input multiple-output (MIMO), orthogonal frequency division multiplexing (OFDM) technology, has been widely used. The FFT Processor is the key module in the all MIMO OFDM communication systems. Therefore, the FFT processor must have the capacity of dealing with the simultaneous multiple data sequences. Adopting several FFT processors to process the simultaneous multiple data sequences, the traditional approach results in lower hardware efficiency and higher power consumption. Therefore, multiple FFT processors integrated to achieve the sharing of hardware resources in order to increase hardware efficiency and to reduce power consumption are the current trend.In this thesis, we proposed a hardware-efficient 128-point FFT processor for the applications in a MIMO OFDM based enhancement of IEEE 802.11n standard. Our processor is adopts the mixed-radix mixed-multipath delay feedback (MRM^2DF) architecture, which provides a higher throughput rate by using the multi-data path scheme, and radix-2 and radix-2^3 algorithm are adopted to reduce hardware complexity. Furthermore, it utilizes the guard interval to increase the capacity of dealing with two parallel data sequences. Thus, the number of parallel paths is extended from four to six. The proposed FFT processor is implemented in UMC 90-nm 1P9M process with core area of 739 x 734 (um)^2 including an FFT processor and a test module. The power consumption is 5.57 mW at 40MHz operating frequency, and SQNR is 40.17dB. At the operation clock rate of 40Mhz, our proposed processor can calculate 128-point FFT with six independent data sequences within 3.2 us meeting the enhancement of IEEE 802.11n standard requirements.