Abstract
In this thesis, specification study, system simulation, architecture design and logic design along with field-programmable gate array (FPGA) implementation of a low complexity and high performance joint transceiver for MIMO Communications is presented. Communication systems using MIMO technique is important because of the potential improvements in transmission rate and/or link performance. Recently, wireless system where the channel state information is available at the transmitter through a feedback link has attracted considerable attention since that can achieves better performance than conventional ones. This thesis presents an efficient and practicable MIMO transceiver in which transmitter antenna selection at receiver is applied to QR detector with GMD precoding through limited feedback channel. The method compensates the deficiency of the GMD algorithm under ill-conditioned channel and improves the BER performance further. From the floating-point simulation results, the proposed transceiver can achieve over 6 dB SNR improvement over the open-loop V-BLAST counterparts at BER=$10^{-2}$ under i.i.d. channel as 4 $\times$ 6 transmitter antenna selection is adopted. Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of $0.5$ per dimension. Simulations are under flat fading and quasi-stationary environment. In view of hardware complexity, several modified schemes and hardware simplifications are presented to save the VLSI design cost. For over $4 \times 5$ antenna selection, the proposed antenna selection scheme can save more than 50\% computational complexity compared with that of the exhausting method. And simple and robust QR detector designed without combining post-processing matrix with satisfactory performance is proposed to reduce computational complexity as well. Moreover, due to practical restrictions, the feedback bandwidth is limited and treasurable, another obstacle to the practical implementation of this scheme is whether or not it performs well when the channel has limited feedback. Hence efficient precoder quantization and reconstruction are also analyzed and evaluated which results in low-rate feedback, low hardware cost, short searching codeword time and less codebook size at the same time. Take a $4 \times 4$ precoding matrix for example, the overhead of feedback bits are substantially reduced from 80 bits with scalar quantization applied to 7 bits that efficient vector quantization is uesd. Finally, a MIMO joint transceiver hardware platform on a Xilinx FPGA is realized to verify the proposed algorithm and architecture. The maximum operating clock rate of the transceiver can achieve about 50 MHz and the corresponding maximum throughput is 120 Mbps. Simulation results and emulation results present correct function and satisfactory performance of our design.