Abstract
In this theses, a design flow for coded modulation that integrates quasi-cyclic low-density parity check (QC-LDPC) codes and iterative detection and decoding (IDD) is proposed. The first major technique in this work is a modified QC-LDPC based density evolution(QCDE). It can indicate the difference between the probability distribution of bits corresponding to individual modulation level of the received symbols, and evaluate the changing of the probability distribution following the structure of the QC-LDPC codes. Comparing the conventional density evolution that can only detect the decoding threshold for BPSK signal, the modified QCDE can evaluate the decoding and detection threshold for IDD receiver with high order modulation, and the effect of the code structure can also be observed. The second major technique is QC-LDPC-based interleaving scheme for error floor lowering. For coded modulation with non-Gray mapping and IDD, an interleaver is required in order to distribute the variable nodes in a single short cycles of QC-LDPC codes into different symbols, or high error floor will be introduced. Take the advantage of the structure of QC-LDPC code, the variable nodes in a single short cycles can be observed via the based matrix and the shift indices, and are mapped into different symbols. Therefore, the interleaver can be removed after a simple column change in the base matrix is applied. The proposed design flow is applied to the construction of the coded modulation combining a length-18396 rate-0.94 QC-LDPC code and the 8-PAM modulation, which is suitable for TLC (triple-level cell) flash memory. Refer to the binary switching algorithm, an optimized non-Gray mapping is selected, then a similar performance can be achieved using a QC-LDPC code with a much smaller degree distribution comparing to that combing the Gray mapping. It shows that, except the low decoding/detection threshold and low error floor, the coded modulation designed using the proposed design flow also has a much low decoding complexity.