Abstract
Forward error correction (FEC) is widely used in wireless communication system, such like broadcast system, mobile communication and WLAN. FEC is used to reduce bit error rate (BER) and improve data quality. There are two code types for FEC design, the first type of FEC is the Reed-Solomon code, whose errors correct capability for both random and burst errors, and the other type is the convolutional code, whose error correct capability for both random bit errors. In addition, between the convolutional encoder and the modulator is a bit interleaver, which protects the convolutional code from severe impact of burst errors and increase overall coding performance. We design a low hardware complexity and high performance Reed-Solomon decoder and reconfigurable Viterbi decoder with different constraint length for multi-standard communications in this thesis. The proposed RS codec processor uses parallel processing to implement syndrome computation and Forney algorithm. Parallel processing improves the operation frequency of RS decoder. We also find the some implementation of finite field multiplier to reduce the area complexity, and choose inversion-free Berlekamp-Massey algorithm for key-equation solver because of the designed concern about hardware complexity decreasing. The proposed reconfigurable Viterbi decoder adds the extra BARG module to improve the flexibility of hardware usage. It only needs 16 cycles to initialize BARG operation, so we can reduce the latency of BARG module. And other feature is we use sharing processing to implement the numbers of constraint length is nine based on Viterbi decoder with constraint length is seven. At finally, we used a Xilinx Spartan3 development board to implement a proposed FEC with a high performance RS decoder, a reconfigurable Viterbi decoder and de-interleaver. The proposed RS decoder can operate at 150MHz; the proposed reconfigurable Viterbi decoder can operate at 20MHz for FPGA implementation.