Abstract
In-vehicle power line communications (PLC) provide a solution for high data communications in the automotive networks without increasing volume, weight and cost of the wiring harnesses. This thesis presents the vehicle power line channel model, which contains multipath fading, impulsive noise, background white noise, and sampling clock offset (SCO) impairments. Also, we propose the design of baseband inner transceiver, which is specifically aimed at the built channel model. The proposed design employs the bandwidth (BW) from 1:8 to 50 MHz and supports BPSK-QAM1024 modulation scheme with maximum data rate 212:83 Mbps. In the transmitter part, the corresponding preamble structure is designed. In the receiver part, it contains packet detection, symbol timing synchronization, sampling clock offset synchronization, channel estimation/equalization, and the nonlinear blanking process for reducing the power of impulsive noise. Functional simulations show the validity of these algorithms and system performance of the proposed transceiver. Under the impulsive noise scenario, the simulation result shows the requirement of SINR (Signal to Interference and Noise Ratio) 72 dB for bit error rate (BER) of 10−3. The ability of impulsive noise resistance, which is provided by the simple non-linear blanking process and large FFT size, under low SINR ( < 64 dB) condition is also shown in the simulation result. The comparison with other works is also obtained. The architecture and logic design of proposed receiver are also presented. To simplified the critical component of whole receiver, a radix-2/4/8/16 single-path delay feedback (SDF) fast fourier transform (FFT) architecture is adopted. It requires only two complex multipliers, and all the trivial multiplications are further simplified by shifting and addition. The cubic interpolator is implemented by Farrow structure to reduce the cost of multiplier. The other components, such as delay correlator, SCO estimator, loop filter, cubic controller and division free hard-demapper, are also designed and presented. Eventually, the functionality of proposed logic design are verified by the test and golden patterns generated form fix-pointed Matlab model NC-Verilog RTL simulation.