Abstract
We present economic models and analysis of built-in self-test (BIST) for logic and memory cores. Typical costs associated with BIST aresilicon area overhead, pin-count overhead, and performance penalty. However, BIST significantly reduces tester-related costs (such as pinrequirement and test data volume) and in many cases, the test time (thanks to at-speed test capability and parallelism). We propose cost and benefit models for BIST, taking into consideration the design verification time and test generation time associated with testability. We propose a novel approach for testability estimation which is used in our models. It analyzes the testability improvement of a logic core with BIST, estimated based on the ISCAS89 benchmark circuits. Experimental results for logic BIST and memory BIST are presented using the proposed models. An IEEE 1149.5 MTM-Bus slave module chip and a march algorithm based memory BIST chip are used as the cases for our evaluation. The results show that a threshold volume exists when BIST is profitable for logic cores---it is not recommended for a higher volume. However, BIST is a good choice for memory cores in general, except when the volume is low. We incorporate the proposed models in our Evaluation System for TEst Engineering Methodologies (ESTEEM) project which started in early 1996. It is a WWW-based VLSI test strategy planning system consisting of a set of models and a test methodology library, plus tools for information management. VLSI project managers and designers can be assisted by ESTEEM when they need to evaluate the costs and benefits of design for testability (DFT).