Abstract
The technology of process is shortened to 65 nanometer, even to 45 nanometer. The functionalities of the same size chip is stronger and stronger. This cause increases of transmission and frequency of electronic products. Therefore, the signal integrity is also affected. So, the current trend is to integrate the chips. The methods of integration are SoC (System-On-a-Chip) and SiP (System-in-a-Package) generally. The bottleneck of SoC and SiP circuit designs are the signal propagation of interconnects. It is because that resistance, inductance and capacitance of interconnects have negative influences on whole circuits. Also, because of the increase of frequency, inductance becomes more and more important.The resistance, inductance and capacitance have negative effects on circuits. Resistance will cause RC delay, thermal effect and skin effect. Capacitance will cause RC delay and cross talk, and the cross talk of inductance will also bring about false switch. These effects of parasitic parameters could not be neglected by circuit designers.Due to the above reasons, correctly extracting the parasitic parameter plays an important role on designing a high speed electronic circuit. Generally we use field solver to get the parasitic parameters; however it is difficult to describe the input of field solver and time-consuming when we use the field solver. Due to the above mentioned reasons, this time we refer to a high integrity, fast, and bring the distributed model to evaluate the signal integrity when it comes to semi-conductor industry. In this software, we aim on 4-layer and 2-layer PCB to design some general interconnects and build responsive resistance and inductance’s data which uses the combination of the interconnects to simulate the metal wire connection in real circuit and design a user friendly graphical user interface. The designer can key in the parameters of the interconnects on the software interface and it will come out quickly to the responsive SPICE netlist and waveform.