Abstract
H.264/AVC is the latest video coding standard jointly developed by ITU-T VCEG and ISO/IEC MEPG. H.264/AVC enhances almost two times coding efficiency than prior video coding standards, but the high computational complexity makes it difficult to decode video in real-time even using high-end central process unit. Sequential CAVLD process is the bottleneck of performance, and mass reference pixel access and high computational complex of intra/inter prediction consume a lot of power. The proposed CAVLD uses the prosperities of codeword, numLZ and TBits, to speed up the table lookup process and decodes more than one syntax element by combining CoeffToken and SIGN stage. Besides, the CAVLD reduces at most 36% power consumption after applying the clock gating to shut down some functional blocks when they are unnecessary. Temp registers are used in the proposed intra/inter predictor to keep the accessed reference pixels and prediction result, and 82% reference pixel access is reduced and at most 7% power dissipation is saved in intra prediction and 66% reference pixels access is reduced and at most 12% power dissipation is saved in inter prediction.