Abstract
A functional test methodology for processor is introduced in this thesis. A processor core based on ARM instruction set is applied as the target processor. When we have functional constraints on individual stage and with proper design rules and partition of processor core, we can use a combinational ATPG tool to generate test patterns for each stage of the processor core. Then the processor can be tested by test instructions. This thesis focuses on single stuck-at functional faults of processor cores. Input constraints of each stage are applied to the ATPG to restrict the input space to functional one. As the constraints increase, more efficient test patterns can be obtained. This method also reduces the test pattern generation time. On the other hand, because this does not change the processor core structure, the proposed methodology has zero speed and area overhead, which is an important feature for timing and area critical designs.