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針對不對稱多核心處理器和非均勻訪存模型架構設計的排程器
Thesis

針對不對稱多核心處理器和非均勻訪存模型架構設計的排程器

張雅婷
Masters, National Tsing Hua University
2011

Abstract

不對稱多核心處理器同指令集異構多核心系統多核心非均勻訪存模型排程機制 asymmetric architecturesingle-ISA heterogeneous architecturemulticoreNon-uniform memory accessscheduling
An Asymmetric Multicore Processors (AMP) system is composed of CPUs with different characteristics, e.g. clock speed, cache capacities, power consumption, occupied area and in-order or out-of-order execution, but the same Instruction Set Architecture (ISA). It is named single-ISA heterogeneous multicore as well. Since the frequency and performance of a processor are developed rapidly, the power consumption and the hot dissipation are the challenges of developing high performance system. Compared to the homogeneous system, AMP could reduce an abundant of power consumption while sacrificing a little performance. With the popularity of hand-held devices, the tradeoff between performance and power consumption is an important issue. Luckily, AMP is extraordinary on this issue.Moreover, the non-uniform memory access (NUMA) architecture is a computer memory design used in multiprocessing, and it could avoid the running processes starving for data easily. As the number of cores is getting bigger and bigger, the NUMA architecture is the trend. Existing schedulers all assumed that the underneath architecture is homogeneous, and therefore AMP and NUMA could not work well with it. As a result, we proposed a new scheduler, NUMA-aware Scheduler for Asymmetric Multicore Processor, to accommodate the next generation of architecture.We implemented a user-level scheduler under Linux system based on the prior Linux scheduler. We have two strategies, (1) Asymmetric-aware Schedule Policy and (2) NUMA-aware Schedule Policy. The average speedup of total execution time of PARSEC benchmarks is 1.36 times faster, and the result is quite good compared to the prior studies.

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