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針對二進位加法器之快速同位元預測遞迴進位遮罩方法
Thesis

針對二進位加法器之快速同位元預測遞迴進位遮罩方法

李仲益
Masters, 國立清華大學, 電機工程學系
1997

Abstract

二進位加法器 同位元預測
The addition of two operands is a basic building block for many arithmetic logic units. The reliability of it can be supported by the parity-checking method. Langdon et al presented the parity prediction scheme based on the concept of "Carry-look-ahead" In Vassiliadis et al work, the parity prediction based on the concept of "Carry-look-ahead" and the concept of "Carry-select". Both of them have the drawbacks. In this thesis, the recursive carry-masking method is proposed to improve the previous parity prediction works. The novelty of this method is to utilize the characteristic of the parity in the process of prediction. As a result, the effect of the carry can be masked during the parity prediction. Moreover, the recursive method also simplifies the parity prediction circuitry. In theoren comparisons, the proposed circuitry reduces the area overhead up to 27% and reduces the operation time up to 55%.

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