Abstract
The Self-testing of an embedded processor core in a system-on-a-chip (SOC) by using its own instruction sequences has several potential benefits which include natural application of functional vectors at-speed, low DFT overhead, and better power and thermal management during testing. However, synthesizing a software test program for an embedded processor to target manufacturing defect is not a trivial task. It requires both gate-level ATPG and test program synthesis with tight integration. In this thesis, a self-testing methodology of functional path delay fault on embedded processor is proposed. Given the instruction set-architecture, and gate-level netlist, test program can be generated by using test program synthesis with constraints. The experimental results for a pipeline processor indicate that the self-testing methodology is useful with delay test ATPG and customized functional test.