Abstract
Recently years, the clock frequency of chips is more faster than before. There are some problems of testing those faster chips. BIST approach is more important because it embedded the test hardware into chips. Therefore, it can solve the problem of speed of ATE is much slower than circuits. The other problem is that the time-related faults,i.e, delay faults. However, there are still some problem of BIST and delay fault testings. In this thesis, we want to generate all deterministic delay fault test patterns which are generated by SAT-based ATPG tool with minimum hardware cost. We propose a heuristic to achieve this objective. We use the reconfigurable LFSR instead of generic LFSR. Finally, we show the experimental result of SAT-based ATPG and use heuristic for transition fault test patterns and path delay fault test patterns.