Abstract
In this paper, a functional path delay fault test flow is proposed for automatically extracting the constraints and generating the functional test patterns for processors and could be extended to ASICs. The Self-testing of an embedded processor core in a system-on-a-chip (SOC) by using its own instruction sequences has several potential benefits which include natural application of functional vectors at-speed, low DFT overhead, and better power and thermal management during testing. The functional constraints are generated by processor architecture and instruction set, and these constraints are applied to generate functional test patterns stage by stage. Then, a test program is synthesized by test patterns and processor architecture. Note that each step in the proposed functional test flow is automatic without manual operation. The Parwan processor is applied to demonstrate the test flow.