Abstract
Speech communication is most essential and common service in telecommunication. Due to the limited bandwidth of the practical communication network, various speech compression standards are developed to alleviate the transmission overhead. In order to consider both the speech quality and the compression ratio, compression standards can only be implemented by employing very complex algorithms which make the performance of decoding processing inefficient. Traditional RISC processors are compiler-friendly and highly efficient in handling control type of applications. However, in the case of executing multimedia applications (ex: video, audio, speech program) which need to execute huge amount of computations iteratively, we won’t obtain a satisfied performance by employing a RISC processor to deal with the multimedia applications. This thesis proposes a new application-specific RISC architecture for speech decoding processing. The new architecture is designed to improve the performance of processing G.729 speech decoder. We develop some enhanced hardware components to build the new architecture. These components are implemented in synthesizable Verilog HDL and successfully synthesized by Synopsys Design Compiler as well as TSMC 0.35μm target library. By integrating these enhanced hardware components into the traditional RISC architecture, we successfully develop the new RISC architecture with the capability of efficient speech decoding processing. According to our simulation result, we found that the application-specific RISC architecture can achieve about 52% performance improvement than the traditional RISC architecture. We believe that it is a lower-cost and efficient solution for the platform which needs to take care of control type of applications and speech decoding application simultaneously without employing an additional and costly DSP.