Abstract
In this thesis, we propose a linear programming-based incremental floorplanning algorithm to minimize the I/O signal skew for flip-chip design. In the linear programming, we add three types of constraints. The topological constraints are used to keep the legality of the floorplan. The skew evaluation constraints are used to evaluate the I/O signal skew. The wirelength restriction constraints are used to restrict wirelength increase when minimizing the skew. Experimental results show that I/O signal skew can be improved from 10% to 31%, and the increase of total wirelength can be controlled in an acceptable range or even improved.