Abstract
Abstract The Static Random Access Memory (SRAM) is an important storage element for the embedded system and generally used today. The sense amplifier of SRAM is utilized to speed up the read operation so that it is a critical influence to the output. The input signals of the sense amplifier are very weak and determine if the sense process succeed or not so it is difficult to measure. We need an accurate and valid circuit to reach the goal. With it the measurement process is automatic and only the lower-end test machine is need. Besides, a new fault model IVDF (insufficient voltage difference fault) is proposed to model the behavior of SRAM cell. We can detect the faulty cell and locate it. The proposed circuit is simulated with 1-K-bit SRAM by using the UMC 0.18um 1P6M Mixed-signal CMOS process.