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鍺掩埋通道與低溫沉積堆疊電荷捕捉層在多晶矽奈米線通道之快閃記憶體元件特性研究
Thesis

鍺掩埋通道與低溫沉積堆疊電荷捕捉層在多晶矽奈米線通道之快閃記憶體元件特性研究

黃建邦
Masters, 國立清華大學, 工程與系統科學系
2015

Abstract

掩埋通道 電荷捕陷式快閃記憶體 多晶矽 奈米線 Buried channel Charge-trapping (CT) flash memory Poly-Si Nanowire
With the recent development of Big Data, the demand of nonvolatile memory increases rapidly. Therefore, nonvolatile memory devices of high storage density with high performance and reliability are necessary. In order to improve the efficiency, high- concentration germanium buried channel is considered as a promising way to enhance the performance, while preserving the scaling-down ability. This thesis proposes an implementation of Ge buried channel on the surface of poly silicon nanowire channels and investigates its electrical characteristics. Three experiments are carried out to test the performance of flash memory devices with the proposed the IM and JL mode components. In the first experiment, germanium is grown on nanowire channel of inversion mode flash memory device. Three different conditions are compared: 1) the growth of Ge and silicon cap-layer, 2) the growth of SiGe and silicon cap-layer, and 3) devices without any growth. Results show that devices with Ge growth have the fast programming and erasing speed. No obvious differences of retention characteristics were seen among the three conditions. The devices with epitaxial growth (condition 1 & 2) exhibit better endurance characteristics because their faster P/E speed reduces the damage of tunneling layer. The second experiment studies low temperature formed HfO2/SiNx stacked trapping layer on three channel structures described in the first experiment. The nitride thin film was deposited by inductively coupled plasma chemical vapor deposition at 450 ℃ in order to reduce thermal cycles in fabrication processes of the devices with Ge containing, which achieves the enhancement of P/E speed and endurance. Results of the second experiment show that the low temperature formed HfO2/SiNx stacked trapping layer can further improve the retention characteristics as compared to results in the first experiment. The third experiment investigates junctionless nanowire flash memory devices with stacked trapping layer in the second experiment. The junctionless devices with Ge buried channel and those without ones are compared. Results show that whatever modes (JL / IM) they are, the program, erase speed and endurance performance can be effectively improved by buried channel. The retention characteristics of devices with buried channels can be still similar as compared to those without ones.

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