Abstract
In this thesis, an on-chip circuit is proposed to measure the peak-to-peak values of worst-case period jitter in phase-locked loops (PLLs) and contains coarse-tune and fine-tune processes. The Coarse-tune process delays the previous rising edge about one clock period to compare with the next adjacent one. The fine-tune process increases or decreases a small timing difference between these adjacent edges to track the peak or valley values of jitter. The proposed circuit solves the problem that a jitter-free reference clock is required to measure the jitter. The circuit is simulated by HSPICE with a 1.8V 0.18um CMOS process. The proposed circuit can operate at the range of 1.12GHz to 2.2GHz with resolution of 7.98ps and measurement error less than 4ps. Compared with other methods, the proposed circuit’s measuring speed is much faster (5 folds) with about 12.4% area overhead.