Abstract
This thesis proposes a method for phase-locked loop diagnosis. PLL plays a very important role in communication systems in present times, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield and achieve cost reduction, it is important to locate the faulty block when it does not meet the specifications as expected. Unlike in the domain of digital IC testing, where structural test methods such as scan-tests and build-in self testing (BIST) have become a common practice, testing of mixed-signal ICs in a structured way is still in its infancy. That is, although BIST for digital IC’s is widely used,manufacturers of mixed-signal IC’s (MMIC) are still searching for an appropriate BIST solution. In the thesis, a method for PLL fault location is presented. The diagnosis method will be introduced step by step, from intuitive ways to the complicated ones. First, a dictionary for looking up for the faulty situations will be created. After that, the cause of the corresponding faulty response will be analyzed. Then, the additional circuit will be added to achieve the faulty block location, which includes several switches and input stimulus. The node for injecting stimulus should be carefully choose not to cause too much loading changing. From the above description, the proposed method can efficiently identify the faulty block of the PLL. The additional circuits are added to the main PLL circuit for simulation level to guarantee the stability of the whole circuit. Finally, the whole circuit is simulated will TSMC 0.18-μto demonstrate the feasibility.