Abstract
Phase-locked loop (PLL) plays an important role in communication and computer systems because PLL affects the speed and performance of the system. In this thesis, besides focusing on the analysis of jitter, lock detector circuit is designed to detect whether the PLL is locked or not; in the issue of energy saving, we design the control signal PDM (Power Down Mode) to turn off the PLL in power down mode when the system does not need it. A PLL is implemented in SMIC 0.13μm 1P8M CMOS process. The output frequency range is from 62.5MHz to 1GHz at 1.2V supply voltage, while the oscillation frequency of voltage controlled oscillator is from 500MHz to 1GHz. Control signals are available to change the divisor of feedback frequency divider. The peak-to-peak jitter and RMS jitter of the PLL are 105ps and 13.39ps at 960MHz, respectively. The power consumption of the chip is 14.3mW at 960MHz and the core (1.2V supply) power consumption of core power is 0.516mW in power down mode. The area of core circuit is 520um×460um. From simulation, the locking time of the PLL is no more than 7us. In the process of measuring the chip, we observed significant impacts of power and input phase noise on the output signal of the PLL. Therefore, we simulated and analyzed the PLL with noisy inputs, especially for the phase frequency detector (PFD) and the voltage controlled oscillator (VCO). These noises resulted in large cycle-to-cycle jitters which is critical to PLL’s applications. A large cycle-to-cycle jitter can cause the system to fail. As a result of our extensive simulation and analysis, we developed equations to predict the max cycle-to-cycle jitter.