Abstract
This thesis presents an on-chip phase-locked loops (PLLs) jitter timing measurement design that the expected deviation from the specification and the average jitters can be measured. Examining the measured signals whether they conform to the specification, the proposed circuit is operated at every cycle of the PLL’s reference frequency without using an extra sampling clock and provides a robust result and low area overhead. A series of pulses with average length of 100-ps is injected in the proposed circuit, and the test results show about 8% measurement errors.With lower area overhead, the proposed design can measure accumulated jitter and give a warning signal if a clock’s jitter over a specific value. To verify the correctness of the design, the proposed circuit is simulated by HSPICE in a standard 0.18-um CMOS technology.