Abstract
In this thesis, we present an on-chip circuit to measure the worst-case period jitter induced by noise for phase-locked loops (PLLs). The circuit uses a digitally controlled delay line to track the extreme period width of the measured signal, thus the worst timing error of the signal can be derived. SPICE simulation results, using 0.18μm CMOS process, show less than 5.2ps (0.7LSB) measurement error at the operation frequency ranging from 850M to 2GHz. Another circuit, for period jitter measurement, is also provided. It uses two-stage vernier oscillators to transform period jitter of the measured signal into digital words. SPICE simulation results, using 0.18μm CMOS process, show less than 8ps (0.8LSB) measurement error at the operation frequency ranging from 800M to 2.5GHz.