Abstract
Clock networks a ect the performance and property of VLSI circuits greatly. Power reduction issue for the clock network becomes an active research area since a large portion of power is dissipated on clock networks. Clock gating is an e ective power reduction technique in sequential circuits. In this work, we propose a fast topology generation algorithm that feeds to zero-skew gated clock network construction. It considers the physical locations, input capacitances, and activity patterns of clock sinks in topology generation stage. Therefore, our algorithm generates an appropriate topology for gated clock routing engine. we also extend the bu ered/gated models in our works. The experiment results show that our approach gains 4%-10% improvements on power saving against previous works.