Abstract
The thesis reports the design and fabrication of 4H-SiC double implant MOSFET with a novel ion implantation masking process, which gets rid of the metal mask in previous approaches. This new process is therefore compatible with industrial MOSFET process since it eliminates the risk of metal contamination. Combining the self-aligned oxidation process and the self-aligned ohmic contact process, the device cell pitch can be narrowed and hence the specific on resistance is expected to reduce significantly. From the experiment results, the best RON,SP is 85 mΩ*cm2, extracted when Vg = 20 V, and Vd = 1 V on a device with the longest effective channel width and a device with the smallest active area, with the JFET length being 5 μm. The best breakdown voltage measured in this work is 2240 V for a 30 μm drift layer thickness, about 60% of the ideal breakdown voltage. From simulation results, it is attributed to the incomplete activation at 1650℃ anneal, which is estimated about 60% at that temperature.