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電荷缺陷儲存式快閃記憶體側向位移之模型分析
Thesis

電荷缺陷儲存式快閃記憶體側向位移之模型分析

古依純
Masters, 國立清華大學, 電子工程研究所
2009

Abstract

快閃記憶體 缺陷 側向位移 flash memory trap lateral migration
Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lowing operating voltage and two-bit storage. However, it also a great challenge for that the local distributions of trap charges will be lateral migrated after thermal various or endurance operation. Since the gate length of the cell devices are continued to scale down, it is crucial to realize the impacts of lateral migration on device characteristics for the programmed and the erased SONOS cells, specially the variations of threshold voltage. In this paper, using diffusion equation to realize the retribution of trapped charge, and then developing the model from gate voltage equation to provide a sound understanding of threshold voltage variations due to lateral migration. Through two-dimensional TCAD simulator MEDICI, the trapped charges are distributed uniformly within the nitride layer. And the conservation of the total trapped charges is assumed in this study. The characteristic lateral migration lengths are used to indicate the degree of lateral migration. Compare the results between the simulation and the modeling to analysis what is the reason in the difference. Eventually, we hope to develop a theoretical model to explain the retention loss characteristics by lateral-migrated trapping charges.

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