Abstract
In this paper, a new asymmetric full logic-compatible transistor which has significant difference between forward-read and reverse-read current has been proposed. This asymmetric device is apply to Static Random Access Memory ( SRAM ) cells, enhancing their read and write performance. Asymmetric transistor is generally formed by changing the doping level of LDD, pocket implant on one side of a MOSFET. By block the LDD and pocket implant at the drain side with the LDD mask, an asymmetric device with different drain and source doping structure can be obtained. In addition to designing and implementing the asymmetric transistor, this study analyzes its current characteristics. From that, a device model describing the asymmetric behavior is built. Then, in order to reduce the read disturb and promote write capability, two access transistors in a SRAM cell is replaced by the asymmetric transistors. Lower accessing current in SRAM read operation, increases the Read Static Noise Margin ( RSNM ) and decreases the opportunity of read disturbs. In the meanwhile, asymmetric device as the access transistor can provide larger current during write operation, which increases the Write Noise Margin ( WNM ) and leads to more stable data.