Abstract
The current market trend in electronic devices leans toward the use of small-sized and multi-functional devices. In particular, package design technologies like Wafer Level Package and Multi-Chip Module have been the widely used. With the combination of these two package designs, the Quasi-Wafer Level Multi-Chip Module structure which uses wafer-level technology to deposit the redistribution layer is discussed in this study. We use the finite element analysis software ANSYS® to discuss the thermal performance and embed metal line reliability. The results indicate that the polymer material in this package is the major factor which influences thermal efficiency and the embedded trace reliability in the structure. First, we probe into the thermal property of equivalent laminated structure. Then we use this equivalent structure to simplify the finite element model and carry out the finite element thermal analysis. Furthermore, we use 2D and 3D finite element models to respectively simulate the embedded trace behaviors upon thermal loading, and discuss the reasons behind metal line destruction. Finally, we design some thermal and reliability enhanced structures based on these results. Our study’s results indicate that the convection boundary is the major factor of the equivalent trace layer’s reasonability. When the lamination layer in the package structure has only a few boundaries that contact with ambient air, the thermal conductivity of this equivalent region could be decided through mixing with its volume ratio and suit for heat transfer finite element problem. The power amplifier is the main heat source in this package, so replacing the adhesive with a heat spreader would improve the thermal performance from the chip to the package’s surface. Due to the package’s limitation on its heat convection ability, building a thermal via to create a new thermal path from the chip carrier to PCB would enhance the thermal performance of this package. Due to the CTE mismatch among the chip, the trace and the dielectric material, the embedded metal line surrounding the chip would induce stress concentration under thermal loading, especially at via structure. The via on chip should be removed from the die edge but should not to go deep into the chip. The stress concentration on the via caused by the expansion of the dielectric material could be reduced by using curved trace. Furthermore, to create a heat spreader in the board level structure might influence seriously the reliability of the via on chip. Correspondingly, the reduction of chip thickness would improve the reliability of the via structure.