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高介電材料於高遷移率砷化銦鎵:達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發
Thesis

高介電材料於高遷移率砷化銦鎵:達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發

邱漢欽
Masters, National Tsing Hua University
2010

Abstract

砷化鎵砷化銦鎵高速電子原子層沉層高介電界面陷阱態密度三五金氧半電晶體三五族半導體製程自動對準 GaAsInGaAshigh mobilityatomic-layer-deposition (ALD)high-kinterfacial density of statesIII-V MOSFETConductance methodQuasi-state CVFermi-level movement efficiencyIII-V processSelf-alignedICP-RIE
Atomic-layer-deposited Al2O3 on In0.53Ga0.47As with short air-exposure between the oxide and semiconductor deposition without any InGaAs surface treatments has shown negligible frequency-dispersion capacitance-voltage (CV) characteristics in the depletion and accumulation region, and well-behaved frequency-dependent inversion curves. The interfacial density of states (Dit) of the metal-oxide-semiconductor capacitor (MOSCAP) was determined by the Terman method and the conductance method. The Dit distribute over the bandgap of In0.53Ga047As in “U”-shape giving lower Dit values near the mid-gap were obtained about 5×1011-3×1012 eV-1cm-2. By the conductance method, however, the Dit values were adopted as the authentic values and the Dit close to the mid-gap is about 3×1012 eV-1cm-2. The quasi-static CV characteristics indicate a high efficiency of 63% for the Fermi-level movement efficiency near the mid-gap.On the basis of the high quality Al2O3/InGaAs interface, self-aligned enhancement-mode (E-mode) inversion-channel InxGa1-xAs (x=0.53 and 0.75) n-MOSFETs using atomic-layer-deposited Al2O3 as the gate dielectric have been demonstrated. Devices with lower dopant activation temperature (DAT) and higher indium content channel show better output DC characteristics. A low subthreshold swing ~ 103 mV/dec was obtained from the In0.75Ga0.25As MOSFETs with DAT of 600oC; furthermore, a maximum drain current (IDS) ~ 1.1 mA/μm was measured at a drain-to-source voltage of 1 V from a 350-nm gate-length device, the highest value among all enhancement-mode inversion-channel n-MOSFETs using InGaAs as the channels and ex-situ grown high-□ dielectrics. In addition, device optimization including TiN gate metal etching by ICP-RIE, channel doping, S/D implantation, and channel engineering were also studied in this work.

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