Abstract
Due to the rise、development and wide application of power devices, LDMOS with planar structure in one of them can integrate high voltage device and low voltage device into the same chip efficiently. Hence, it becomes the major driver IC because of this reason. One of the characteristic of LDMOS is its low dopant region that can supply large resistance, is the key point of high breakdown voltage. And to have the low on-resistance and high breakdown voltage at the same time becomes the desired request of LDMOS design. The traditional HV device used the principle of Reduced Surface Field (RESURF) can make the integration of circuit to be realized on a thin epitaxial layer. But the electrical characteristic of device is very sensitive to the changing of process parameters so that it is harder to design. For example, the increase of breakdown will produce high on-resistance. Hence, the rated current is limited relatively. In this thesis, the increase of breakdown and low on-resistance are performed by introducing internal field ring、P buried layer and double metal layers into LDMOSFET structure. Finally, we use computer simulation to obtain the optimum fine tune parameters of process.