Abstract
In this paper, we propose a highly efficient and accurate Multi-Core Instruction-Set parallel simulation (MCISS) approach by synchronizing timing before each synchronization function call. We greatly improve the applicability of the state-of-art critical-section-level simulation approach with a generic blocking/non-blocking send/receive model covering all types of synchronization functions. To reduce synchronization overhead, we also introduce optimization methods such as hybrid scheduling technique and provide an analysis tool for host platform choice for best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 272 MIPS, which is 3 times faster than the shared-variable-level approach while producing accurate timing and functional results equal to those from cycle-accurate approaches.