Abstract
In this thesis, we present a timing-driven architecture and component selection method for high-performance FIR designs. We develop an FIR generator that can generate Verilog-based RTL design specifications on the fly by determining FIR’s structure, component types and their delay budgets subject to satisfying the given timing constraints. By integrating the FIR generator and a number of commercial RTL/logic and physical synthesis tools, we develop a design environment for high-performance FIR designs. Experimental results are reported to demonstrate the effectiveness of our proposed method.