Abstract
In this thesis, we present a custom-cell identification method for high-performance datapath designs. Our proposed method consists of two phases: (1) the maximum-timing-driven RTL/logic synthesis and (2) the custom-cell identification. In the first phase, we use a commercial synthesis tool to convert an RTL design into a gate-level design with an achievable fastest timing, and then apply the MISA-based slack assignment and re-synthesis process to minimize the area cost. In the second phase, we present a branch-and-bound algorithm and a heuristic to identify the module/cell set that needs to be customized in order to satisfy the given timing constraint. Experimental results have been presented to demonstrate the effectiveness of our proposed method.