Abstract
The Advanced Encryption Standard (AES) was proposed by National Institute of Standard and Technology (NITS) of the United States in 2001. Our AES design supports Electronic Code Book mode (ECB), Cipher Block Chaining mode (CBC), Counter mode (CTR), and Counter with CBC-MAC mode (CCM) operation modes. After analysis, 2-stage pipeline architecture is cost-e±cient for most modes. In recent year, lots of research of AES is proposed. SBox, the heaviest component in AES, is always implemented in Look-up-table (LUT) or composite ‾eld arithmetic. But the LUT based SBox can not be shared in encryption and decryption. In our design, we decompose the SBox to multiplicative inverter and a±ne transformation, and only implement the inverter in LUT. Therefore, the SBox can be shared between encryption and decryption to decrease the overhead. In addition, the decomposed SBox will need only 128 bit pipeline register at the balanced pipeline position in datapath which is less than 192 bit in composite ‾eld arithmetic SBox. Besides the multiplicative inverter, our a±ne transformation is also merged into the MixColumns(), which performs a matrix multiplication in AES algorithm. In addition, a re-timing technique is applied to reduce the area and critical path. Our AES core can operate in 128, 192, 256 bit key, and the round key is generated on-the-°y. Using a typical 0.18 ¹m CMOS technology, 250 MHz clock rate is achieved, and the throughput for 128 bit key is 3.2 Gbps. Using a typical 0.13 ¹m CMOS technology deals a better clock rate of 333 MHz, and the throughput for 128 bit key is 4.27 Gbps. Besides, the power and testability is also considered. The power consumption is estimated as 113.4mW in 0.18 ¹m process, and 43.78mW in 0.13 ¹m process. The fault coverage is 98.38% with 212 test patterns. The gate count of our AES core is 78.8K gates using 0.18 ¹m CMOS technology, and 91.1K gates using 0.13 ¹m CMOS technology.