Abstract
The AES (Advanced Encryption Standard) algorithm is a new standard algorithm of symmetric-key cryptography system. In order to replace DES algorithm, the Rijndael’s algorithm was selected as the Advanced Encryption Standard (AES) by the National Institute of Standards and Technology (NIST). Cryptographic applications are often applied to application specific integrated circuit (ASIC) design as it is trusted in sufficient security level. However, fixed hardware implementations become more and more insecure because it is impossible to update or upgrade in response to new security threats. For high security level, a reconfigurable S-box utilized RAM based design is constructed in our AES design. And the reconfiguration of S-box can be generated by using our previous proposed pseudo random number generator (PRNG). The PRNG utilized to generate random numbers can construct the look-up table of S-box dynamically. The embedded memory of FPGA is exploited for the reconfigurable S-box in our proposed architecture. Using FPGA with embedded memory is the most cost-effective for RAM based design because for the balance of memory and logic resource. Mix/InvMix Column dominates both in the logic resource and the critical delay in AES hardware implementation with direct mapping S-boxes. The integrated Mix/InvMix Column circuit based on the proposed decomposition method optimizes the area and the delay. Theoretically, in architecture level, the proposed short-path circuit reduced the area up to 42% with the same 5 XOR gates delay in critical path. The FPGA of Altera Stratix family EP1S25F780C5 is used to implement our AES design. A 70 MHz clock is achieved, and the throughput is 0.898 Gbps for 128-bit keys.