Abstract
The AES (Advanced Encryption Standard) algorithm is a new standard of symmetric- crypto system. It was announced by National Institute of Standards and Technology (NIST) of the United States to replace the DES (Data Encryption Standard) algorithm and many hardware implementations have been proposed. Most of these hardware design implemented the key component, S-box, by the costly memory base method. We propose an eÆcient hardware implementation of the AES algorithm, with key ex- pansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0:35m CMOS technology, a 200MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5K gates.