Abstract
The speed of a digital arithmetic processor for addition, subtraction, multiplication, and division is heavily dependent on the speed of the adders used in the system. In the system on chip (SoC) generation, faster speed and smaller area electric devices are required to build the large circuit. In order to increase the speed of ALU, increasing the speed of adders is a useful and efficient method. This thesis proposes a segment parallel adder (SA) as a choice for various high speed addition techniques. This segment parallel adder consists of horizontal and vertical segments those are executed the addition in parallel. When the horizontal segment starts addition from the LSB to the MSB, the vertical segment is also active simultaneously from the top to the bottom such that the time delay from the top to the bottom should be equal to that of the horizontal segment of the carry propagation from the LSB to the MSB. In this way, an optimal matched addition is obtained. From the simulation result, the proposed variable segment parallel adder reveals the fewest delay and fastest speed. The delay of the variable segmented parallel adder can be reduced to 29% compared with the CSA at the cost of larger area of 72%. The AT2 in this case is also reduced to 14%.