Abstract
本論文旨在研究乾蝕刻技術在微機電領域矽微結構(silicon micro structure)的應用。藉由黑色矽深蝕刻法(BSM,Black Silicon Method) [1]。以及加側壁保護層深蝕刻(ASP, Additional Sidewall Passivation)的方法[2]。在矽材料上蝕刻深度大於10微米，非等向性( anisotropy)約0.98的深槽。有別於利用超低溫(約-120℃)[3],低壓(<10 mT)[4],以及利用高電漿密度[5]蝕刻的活性離子蝕刻(Reactive Ion Etching, RIE)技術。本論文的研究是利用低電漿密度的活性離子蝕刻反 應器在室溫，一般壓力(~100mT)的反應條件下，進行蝕刻。蝕刻的氣體採 用六氟化硫(SF6),氧氣(O22)，以及三氟氫化碳(CHF3)三種氣體混合的系 統。利用ASP的基本理論與實驗結果，解決BSM深槽表面內縮(surface indention )問題。深蝕刻過程中的高寬比依賴蝕刻(ARDE, Aspect Ratio Dependent Etching)現象在ASP的模型中亦可得到適當的解釋與最佳化。 與BSM相比，ASP方法針對深蝕刻提供了更可靠的製程方法與確定的實驗理 論。 Etching of highly anisotropic deep silicon trench is achieved by the combination of black silicon method (BSM) and additional sidewall passivation (ASP) techniques .The depth is larger than 10 um and anisotropy is 0.98. aspect ratio dependent etching (ARDE) phenomenon is also observed and discussed with ASP model. Without using the additional features such as low temperature (~ -120℃) and low pressure( <10 mT),or high density plasma to RIE, we propose a method to achieve deep silicon etch with vertical sidewall microstructure using ordinary a parallel plate RIE reactor. The concepts of this method come from the BSM and ASP processes. Though BSM has already been proposed as a process sequence to find the most vertical etching condition for common RIE system, there still exist some theory uncertainties and problems