Abstract
This thesis presents the studies of the gate dielectric reliabilities in FinFETs. Two topics are covered in this thesis: time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). The TDDB of N type FinFETs were measured and the oxide trap densities were studied. The gate stress induced leakage currents (SILC) for N-FinFETs are found to be increased by 30% over the fresh devices. As compare to the reported 300% increase in SILC for planar MOSFET, an order of magnitude reduction in the increase of SILC is observed. Thus, FinFETs has a better gate SILC than planar MOSFET. Thermochemical and anode hole injection model are used to study the dielectric breakdown. It appears that both models seem to fit the measured data reasonably good for N-FinFETs. With the use of the thermochemical model, voltage acceleration factor is 6(1/V) and 10 year life-time safety operation voltage shall be under about 1.6V. The NBTI for P type FinFETs is studied along with its interface trap density. After 1000s forward and reverse sweep, the difference in degradation between forward and reverse sweep is small. Moreover, threshold voltage shift has power law dependence ( ) and n=0.2~0.3.