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35.56Gbits/sec Chaos Random Number Generator Supporting 1.2GSamples/sec Noise Generation
期刊文章

35.56Gbits/sec Chaos Random Number Generator Supporting 1.2GSamples/sec Noise Generation

成彬 陳, 聰 陳, 郁翔 黃元豪 黃
IEEE Transactions on Circuits and Systems II: Express Briefs, 卷.70(10), 頁碼.3802-3806
10/2023

摘要

FPGA;random number generator;lorenz system;noise generator

Random number generators (RNGs) and noise generators (NGs) play significant roles in various centralized and decentralized security systems. This brief proposes all-digital FPGA-based RNG and NG based on the chaos system. The proposed chaos RNG (CRNG) adopted Euler method to realize the differential functions of the modifed Lorenz system with a modifed modulo-one unit. The ADC-noise-perturbated initial values are included to generate the random sequences for the proposed CRNG. The proposed chaos NG (CNG) conbines the proposed CRNG with parallel Box Muller processors to generate Gaussian noise signals with the enhanced througput. The proposed CRNG processor and CNG processor were designed and implemented by Xilinx Virtex-7 VC707 FPGA. The proposed CRNG processor achieved a throughput of 35.56Gbits/sec at a clock frequency of 370MHz and the proposed CNG processor achieved a throughput of 1.2Gsamples/sec at a clock speed of 200MHz. Compared with other state-of-the-art works, the proposed CRNG and CNG processors have not only the highest throughputs but also the best hardware efficiency.

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