65nm CMOS receiver with 4.2dB NF and 66dB gain for 60GHz applications

N.Y. Wang; H. Wu; J.Y.C. Liu; M.-C.F. Chang

doi:10.1049/el.2010.3094

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65nm CMOS receiver with 4.2dB NF and 66dB gain for 60GHz applications

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65nm CMOS receiver with 4.2dB NF and 66dB gain for 60GHz applications

N.Y. Wang, H. Wu, J.Y.C. Liu and M.-C.F. Chang

Electronics Letters, Vol.47(1), pp.15-17

06/01/2011

DOI: https://doi.org/10.1049/el.2010.3094

Abstract

A direct conversion receiver for 60GHz applications is fabricated in 65nm CMOS. It consists of three low-noise amplifier gain stages, an RF mixer, a lowpass filter and a three-stage programmable gain amplifier. An overall minimum noise figure (NF) of 4.2dB and maximum gain of 66dB is achieved by the receiver occupying a core area of 0.26mm ² while drawing 36mA of current from a 1V supply. © 2011 The Institution of Engineering and Technology.

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Title: 65nm CMOS receiver with 4.2dB NF and 66dB gain for 60GHz applications
Creators - without role: N.Y. Wang - University of California, Los Angeles
H. Wu - University of California, Los Angeles
J.Y.C. Liu - University of California, Los Angeles
M.-C.F. Chang - University of California , Department of Electrical Engineering
Publication Details: Electronics Letters, Vol.47(1), pp.15-17
Identifiers: 9957773105306774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Journal article

65nm CMOS receiver with 4.2dB NF and 66dB gain for 60GHz applications

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