This brief presents a cryogenic inverter-based two-fold current reuse with a dual noise-canceling low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of three stages: a current-reuse inverter-based input stage with shunt-resistive feedback and self-body bias (SBB) to mitigate the V_{\mathrm{ th}} increase and boost r_{\mathrm{ out}} under cryogenic temperature. The second stage is the dual auxiliary noise-canceling stage with an additional current reuse parallel transistor to enhance transconductance and suppress the noise of both the main amplifier and auxiliary amplifier. The last stage is a common-source post-amplifier for further gain enhancement. At 4 K, the LNA achieves a measured peak gain (S_{21}) of 31 dB, with a large 3-dB bandwidth from 10 MHz to 2.6 GHz and a minimum NF of 0.1 dB (corresponding to noise temperature T_{N} of 6.8 K) at 0.6 GHz under power dissipation of 8.6 mW. The circuit occupies a core area of 0.117 mm2.
- A 0.01-to-2.6-GHz Two-Fold Current Reuse Dual Noise-Canceling LNA Achieving 6.8-K Noise Temperature for Quantum Applications
- Mahesh Kumar ChaubeyChih-Cheng LinYin-Cheng ChangPo-Chang WuHann-Huei TsaiShawn S. H. Hsu
- IEEE
- 5
- Journal article
- 01/05/2024
- IEEE transactions on circuits and systems. II, Express briefs, Vol.71(5), pp.2504-2508
- English
- 112-2119-M-002-014; 113-2923-E-007-013-MY2 / National Science and Technology Council (NSTC) (10.13039/501100020950)