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A 0.3 V Conductance Based Silicon Neuron in 0.18&null CMOS Process
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A 0.3 V Conductance Based Silicon Neuron in 0.18&null CMOS Process

Meysam Akbari, Safwan Mawlood Hussein, Ting-I ChouKea-Tiong Tang
IEEE Transactions on Circuits and Systems II: Express Briefs
2021

摘要

Capacitance First-order Frequency adaption. Low voltage Low-energy Mathematical model Membrane Membrane potentials Micromechanical devices Neuron Neurons Spike Transistors Electrical and Electronic Engineering
This paper presents a conductance-based neuron that is capable of operating under ultra-low-voltage supplies. The proposed neuron employs a variable-gain low-pass filter to linearly integrate the input spikes onto the membrane capacitance. A positive feedback topology is used to generate output spikes and implement a frequency adaption mechanism. A differential amplifier is as well employed as a comparator to reset the membrane potential and set a threshold voltage to control the spike generator circuit. The mathematical analyses result in a first-order linear equation for membrane current of the neuron. The designed neuron was fabricated in TSMC 0.18 lm CMOS technology with an area of 993 lm2 that consumes 135 fJ/spike under a 0.3-V supply voltage. The experimental results show frequency adaption mechanism and intrinsic chattering, while regular and fast-firing behaviors are achieved by adjusting control parameters.

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