A 0.3 v 10-bit SAR ADC with First 2-bit Guess in 90-nm CMOS

Jin-Yi Lin; Chih-Cheng Hsieh

doi:10.1109/TCSI.2016.2613505

A 0.3 v 10-bit SAR ADC with First 2-bit Guess in 90-nm CMOS

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A 0.3 v 10-bit SAR ADC with First 2-bit Guess in 90-nm CMOS

Jin-Yi Lin 和 Chih-Cheng Hsieh

IEEE Transactions on Circuits and Systems I: Regular Papers, 卷.64(3), 頁碼.562-572

03/2017

DOI: https://doi.org/10.1109/TCSI.2016.2613505

摘要

Low power

low voltage

SAR ADC

Electrical and Electronic Engineering

This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by sqrt 3 /2 in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm ² . The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden's FoM and Schreier's FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively.

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詳細資料

題名: A 0.3 v 10-bit SAR ADC with First 2-bit Guess in 90-nm CMOS
創作者：: Jin-Yi Lin (作者) - Department of Electrical Engineering , National Tsing- Hua University
Chih-Cheng Hsieh (作者) - National Tsing Hua University
學術資源類型: 期刊文章
出版日期: 03/2017
出版資訊: IEEE Transactions on Circuits and Systems I: Regular Papers, 卷.64(3), 頁碼.562-572
語言: 英語

A 0.3 v 10-bit SAR ADC with First 2-bit Guess in 90-nm CMOS

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