Abstract
This paper presents a 0.3V energy efficient 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). A shifted monotonic switching (SMS) procedure is proposed to achieve an average DAC switching energy of 63.75CV2. Two redundant bits are implemented with an error tolerance of pm 12mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in 90nm CMOS with a core size of 250?m×50?m (0.0125 mm2). At 250KS/s and Nyquist rate input, it consumes 52.3nW at 0.3V supply with an achieved SNDR of 51.21dB and a resulting FoM of 0.705fJ/conv.-step.