摘要
This article presents a 12-effective number of bits (ENOB) second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage&null (V-T-V) converter. The proposed NS-SAR ADC uses a V-T-V converter to provide an accurate open-loop gain stage for the active residue process. By relying on the capacitor and current ratios, the gain of the V-T-V converter is inherently PVT-insensitive. Therefore, no calibration is needed, and an aggressive noise transfer function (NTF) can be realized. Moreover, the V-T-V converter consumes only dynamic power, making the ADC more efficient. The proposed design was fabricated in the TSMC 90-nm 1P9M CMOS process with a core area of 429.7 TEXPRESERVE0 90.7 <inline-formula> <tex-math notation="LaTeX">$mu$</tex-math> </inline-formula>m<inline-formula> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula>. At 1-V supply voltage and 10-MS/s sampling rate, the ADC achieved a signal to noise and distortion ratio (SNDR) of 73.8 dB, and the corresponding ENOB is about 12-bit at 625-kHz input signal bandwidth. The total power consumption is 71.4 <inline-formula> <tex-math notation="LaTeX">$mu$</tex-math> </inline-formula>W, resulting in a Walden figure of merit (FoM<inline-formula> <tex-math notation="LaTeX">$_{mathrm{W}})$</tex-math> </inline-formula> and Schreier figure of merit (FoM<inline-formula> <tex-math notation="LaTeX">$_{mathrm{S}})$</tex-math> </inline-formula> of 14.2 fJ/c-s and 173.2 dB, respectively.