摘要
This paper presents a 0.9-V 1.5-mW 150-MS/s 12-bit successive-approximation-register analog-to-digital converter (SAR ADC) in 40-nm CMOS, which achieves a synergistic integration of multi-bit per cycle (M-bit/cycle) and sub-radix techniques with the comprehensive enhancement of speed and error tolerance. The proposed sub-radix-3 architecture uses a merged digital-to-analog converter (DAC) with a two-input comparator instead of the conventional separated DACs (signal and reference DACs) with a four-input comparator to effectively improve the matching performance and the power efficiency. Alternative-reference-switching (ARS) DACs are developed to reduce the total DAC effective switching capacitance by 47.4%. Offset injection technique is implemented to calibrate the comparator offset without the speed and power penalty by eliminating the additional output loading of capacitor array or the extra input pair. The SAR logic of each conversion cycle is simplified into one single tri-latch current mode logic (CML) to directly control the DAC switches which effectively reduces the SAR delay by 2/3. The achieved peak signal to noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR), and Walden FoM are 61.7 dB, 74.4 dB, and 10.3-fJ/conversion-step, respectively.