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A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS
期刊文章

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

Yun-Cheng Jao, Po-Ting Shen, Yen-Po Lin, 秉璇 謝, Pen-Jui Peng 和 Chun-Chang Lu
2025
DOI: https://doi.org/10.1109/JSSC.2025.3562885

摘要

Clock and data recovery (CDR);CMOS;extra- short-reach (XSR);feed-forward equalizer (FFE);four-level pulse amplitude modulation (PAM-4);receiver (RX);time-interleaved analog-to-digital converter (ADC);transmitter (TX)

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1 檢視次數

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