A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

Yun-Cheng Jao; Po-Ting Shen; Yen-Po Lin; Ping-Hsuan Hsieh; Pen-Jui Peng; Chun-Chang Lu

doi:10.1109/JSSC.2025.3562885

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期刊文章

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

Yun-Cheng Jao, Po-Ting Shen, Yen-Po Lin, Ping-Hsuan Hsieh, Pen-Jui Peng 和 Chun-Chang Lu

2025

DOI: https://doi.org/10.1109/JSSC.2025.3562885

Web of Science ID: WOS:001480603000001

摘要

Clock and data recovery (CDR);CMOS;extra- short-reach (XSR);feed-forward equalizer (FFE);four-level pulse amplitude modulation (PAM-4);receiver (RX);time-interleaved analog-to-digital converter (ADC);transmitter (TX)

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2 檢視次數

4 被引用次數 - Web of Science

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本研究成果之相關指標（擷取自 InCites Benchmarking & Analytics）

引用書目主題: 4 Electrical Engineering, Electronics & Computer Science; 4.138 Semiconductor Technology; 4.138.205 RF CMOS Design
Web Of Science研究領域: Engineering, Electrical & Electronic
ESI研究領域: Engineering

詳細資料

題名: A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS
創作者：: Yun-Cheng Jao (顧問)
Po-Ting Shen (顧問)
Yen-Po Lin (作者)
Ping-Hsuan Hsieh (作者)
Pen-Jui Peng (顧問)
Chun-Chang Lu (顧問)
學術資源類型: 期刊文章
出版日期: 2025
語言: 英語
期刊等級: true

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver with Time- Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

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InCites亮點

詳細資料

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