A 43.4-dB gain 7.6-mW 197.5% bandwidth double noise-canceling cryogenic LNA using gain peaking technique for multiple spin qubit readout

This paper proposes a cryogenic stacked inverterbased gain-flattening low-noise amplifier (LNA) with dual current reuse and dual noise-canceling in 28-nm CMOS. The LNA features a current-reuse high-Q gate inductor and cascode inverter-based input stage with shunt-resistive feedback, optimizing wideband input impedance. A cryogenic aware self-body bias (SBB) mitigates Vth and rout variations at cryogenic temperatures. The design incorporates a source-degenerated common-source (CS) main amplifier, followed by current reuse inductor gain peaking cascode dual noise-canceling CS transistors, enhancing transconductance and suppressing noise in both main and auxiliary amplifiers. At cryogenic temperature (4 K), the LNA achieves a measured peak gain (S21) of 43.4 dB, with a large 3-dB bandwidth from 0.02 – 3.2 GHz (197.5 % fractional BW) and a minimum NF of 0.37 dB (corresponding to noise temperature TN of 25.8 K) at 0.7 GHz under power dissipation of 7.6 mW. The circuit occupies an active area of 0.31 mm2 . Index Terms—Cryogenic CMOS, cryogenic aware self-body bias, current reuse, double noise-canceling, gain peaking, lownoise amplifier (LNA), quantum computing, spin qubits.